Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43310 )
Change subject: soc/amd/picasso: Add dummy spinlock for psp_verstage ......................................................................
soc/amd/picasso: Add dummy spinlock for psp_verstage
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled. BUG=None
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h 1 file changed, 17 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h new file mode 100644 index 0000000..5245bd1 --- /dev/null +++ b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ARCH_SMP_SPINLOCK_H +#define _ARCH_SMP_SPINLOCK_H + +#define DECLARE_SPIN_LOCK(x) +#define barrier() do {} while (0) +#define spin_is_locked(lock) 0 +#define spin_unlock_wait(lock) do {} while (0) +#define spin_lock(lock) do {} while (0) +#define spin_unlock(lock) do {} while (0) +#define cpu_relax() do {} while (0) + +#include <smp/node.h> +#define boot_cpu() 1 + +#endif