[coreboot-gerrit] Change in coreboot[master]: rockchip: rk3399: remove the delay for enableing SSC

[Caesar Wang (Code Review)]

Hello Julius Werner,

I'd like you to do a code review.  Please visit

https://review.coreboot.org/19699

to review the following change.

Change subject: rockchip: rk3399: remove the delay for enableing SSC
......................................................................

rockchip: rk3399: remove the delay for enableing SSC

The hang was caused by deassert the reset before, it had been delayed 20us
fixing the hang issue.
So we can remove this delay for now.

Change-Id: I5545377b72eb20b59ceaaca25c78965854bfb919
Signed-off-by: Caesar Wang 
---
M src/soc/rockchip/rk3399/clock.c
1 file changed, 0 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/19699/1

diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 944ca6f..7e205d2 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -356,11 +356,6 @@
 {
    u32 divval;

-	/*
-	 * TODO find the root cause why is the delay needed, otherwise sometimes
-	 * hang somewhere with reboot tests.
-	 */
-	udelay(30);
    assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);

/*