[coreboot-gerrit] New patch to review for coreboot: f0486b1 Exynos5420: tighten up display port delays

[Isaac Christensen]

Isaac Christensen ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6506

-gerrit

commit f0486b187d184523d1b413801d786c278ff9e90e
Author: Ronald G. Minnich 
Date:   Fri Aug 16 19:53:41 2013 -0700

Exynos5420: tighten up display port delays

Shorten a few delays, and make some delays shorter but let the
    loops have a higher termination count (i.e. give it the same
    amount of time to warm up, but check more frequently).

Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43
    Signed-off-by: Ronald G. Minnich 
    Reviewed-on: https://gerrit.chromium.org/gerrit/66156
    Commit-Queue: Ronald G. Minnich 
    Tested-by: Ronald G. Minnich 
    Reviewed-by: Stefan Reinauer 
    (cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a)
    Signed-off-by: Isaac Christensen 
---
 src/cpu/samsung/exynos5420/dp.h          | 2 +-
 src/cpu/samsung/exynos5420/dp_lowlevel.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/dp.h b/src/cpu/samsung/exynos5420/dp.h
index d260c88..4d9d26b 100644
--- a/src/cpu/samsung/exynos5420/dp.h
+++ b/src/cpu/samsung/exynos5420/dp.h
@@ -1187,7 +1187,7 @@ static inline u32 exynos_fimd_get_base_offset(void)
 #define EXYNOS_DP_CLK_ENABLE				(1 << 1)
 #define EXYNOS_MIE_CLK_ENABLE				(3 << 0)

-#define DP_TIMEOUT_LOOP_COUNT		100
+#define DP_TIMEOUT_LOOP_COUNT		1000
 #define MAX_CR_LOOP			5
 #define MAX_EQ_LOOP			4

diff --git a/src/cpu/samsung/exynos5420/dp_lowlevel.c b/src/cpu/samsung/exynos5420/dp_lowlevel.c
index 64a2962..16b9a7f 100644
--- a/src/cpu/samsung/exynos5420/dp_lowlevel.c
+++ b/src/cpu/samsung/exynos5420/dp_lowlevel.c
@@ -452,7 +452,7 @@ unsigned int exynos_dp_detect_hpd(void)
    while (exynos_dp_get_plug_in_status() != 0) {
    	if (timeout_loop == 0)
    		return -1;
-		mdelay(10);
+		mdelay(1);
    	timeout_loop--;
    }

@@ -865,7 +865,7 @@ void exynos_dp_reset_macro(void)
    lwrite32(reg, &dp_regs->phy_test);

/* 10 us is the minimum Macro reset time. */
-	mdelay(1);
+	udelay(50);

reg &= ~MACRO_RST;
    lwrite32(reg, &dp_regs->phy_test);