Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43307 )
Change subject: soc/amd/common: Refactor and consolidate code for spi base ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/43307/6/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/43307/6/src/soc/amd/common/block/sp... PS6, Line 22:
We call to initialize that very early in the PSP verstage, and we can't read the value. […]
Added ASSERT(spi_base)
https://review.coreboot.org/c/coreboot/+/43307/5/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_ctrl.c:
https://review.coreboot.org/c/coreboot/+/43307/5/src/soc/amd/common/block/sp... PS5, Line 33: static inline uint8_t spi_read8(uint8_t reg)
Ack
Removed since I changed back to spi_get_bar()
https://review.coreboot.org/c/coreboot/+/43307/6/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi_ctrl.c:
https://review.coreboot.org/c/coreboot/+/43307/6/src/soc/amd/common/block/sp... PS6, Line 33: static inline uint8_t spi_read8(uint8_t reg)
Yes, I was acknowledging the comment. I would have marked it 'done' if I had done it. […]
Addressed.
https://review.coreboot.org/c/coreboot/+/43307/6/src/soc/amd/common/block/sp... PS6, Line 35: return read8((void *)(spi_base + reg));
Will change back.
Done.