Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31902 )
Change subject: soc/intel/cannonlake: Clear PMCON status bits
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Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c
File src/soc/intel/cannonlake/pmutil.c:
https://review.coreboot.org/#/c/31902/3/src/soc/intel/cannonlake/pmutil.c@14...
PS3, Line 146: pmc_clear_suspwrflr
Does FSP rely on these values? If yes, what for? Ideally I was thinking of doing this in pmc_init […]
I looked at the FSP code, FSP is using these bits to determine bootmode in PreMem stage. PWR_FLR, GBL_RST_STS and HOST_RST_STS bits are cleared in FSP Post PCI enumeration. We can clear it in pmc_init(), but to be on safer side it would be good to do it in pch_finalize() as Rizwan suggested.
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Gerrit-Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
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