Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49490 )
Change subject: intel/xeon_sp/*/include/soc/pci_devs: Fix code style ......................................................................
intel/xeon_sp/*/include/soc/pci_devs: Fix code style
- use tabs instead of whitespace; - remove unnecessary zeros in hex values.
Change-Id: I767391fed3df41234dd116fabea0427f366068c3 Signed-off-by: Maxim Polyakov m.polyakov@yadro.com --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h 2 files changed, 151 insertions(+), 151 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/49490/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 848cb48..93a283e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -6,48 +6,48 @@ #include <device/pci_def.h> #include <types.h>
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) -#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) -#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) -#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif
-#define SAD_ALL_DEV 29 -#define SAD_ALL_FUNC 0 -#define SAD_ALL_PAM0123_CSR 0x40 -#define SAD_ALL_PAM456_CSR 0x44 +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44
-#define PCU_IIO_STACK 1 -#define PCU_DEV 30 -#define PCU_CR1_FUN 1 +#define PCU_IIO_STACK 1 +#define PCU_DEV 30 +#define PCU_CR1_FUN 1
-#define PCU_CR1_BIOS_MB_DATA_REG 0x8c +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
-#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x1
-#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12)
-#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
#define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 @@ -65,23 +65,23 @@ #define VTD_MMIOL_CSR 0xdc #define VTD_ME_BASE_CSR 0xf0 #define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C +#define VTD_VERSION 0 +#define VTD_CAP 0x8 +#define VTD_CAP_LOW 0x8 +#define VTD_CAP_HIGH 0xC #define VTD_EXT_CAP_HIGH 0x14 #define VTD_LTDPR 0x290
/* CPU Devices */ -#define CBDMA_DEV_NUM 0x04 +#define CBDMA_DEV_NUM 0x4
-#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 +#define VMD_DEV_NUM 0x5 +#define VMD_FUNC_NUM 0x5
#define MMAP_VTD_CFG_REG_DEVID 0x2024 #define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 -#define VTD_FUNC_NUM 0x0 +#define VTD_FUNC_NUM 0
#if !defined(__SIMPLE_DEVICE__) #define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) @@ -89,39 +89,39 @@ #define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif
-#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x04 +#define APIC_DEV_NUM 0x5 +#define APIC_FUNC_NUM 0x4
/* PCH Device info */
-#define XHCI_BUS_NUMBER 0x0 -#define PCH_DEV_SLOT_XHCI 0x14 -#define XHCI_FUNC_NUM 0x0 +#define XHCI_BUS_NUMBER 0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0 #define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2)
-#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
-#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 +#define HPET_BUS_NUM 0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0
-#define PCH_IOAPIC_BUS_NUMBER 0xF0 -#define PCH_IOAPIC_DEV_NUM 0x1F -#define PCH_IOAPIC_FUNC_NUM 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 +#define PCH_IOAPIC_DEV_NUM 0x1F +#define PCH_IOAPIC_FUNC_NUM 0
// ========== IOAPIC Definitions for DMAR/ACPI ======== -#define PCH_IOAPIC_ID 0x08 +#define PCH_IOAPIC_ID 0x8
// DMI3 B0D0F0 registers #define DMI3_DEVID 0x2020 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 39f6212..29aa02c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -19,16 +19,16 @@ ((uint32_t)dev >> 12) & 0x07, #reg, reg, \ pci_mmio_read_config32(dev, reg+4), pci_mmio_read_config32(dev, reg))
-#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) -#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) -#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) +#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) +#define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) -#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif
#define SAD_ALL_DEV 29 @@ -36,42 +36,42 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define SAD_ALL_PAM456_CSR 0x44
-#define PCU_IIO_STACK 1 -#define PCU_DEV 30 -#define PCU_CR1_FUN 1 +#define PCU_IIO_STACK 1 +#define PCU_DEV 30 +#define PCU_CR1_FUN 1
-#define PCU_CR0_FUN 0 -#define PCU_CR0_PLATFORM_INFO 0xa8 -#define PCU_CR0_P_STATE_LIMITS 0xd8 -#define P_STATE_LIMITS_LOCK_SHIFT 31 -#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) -#define PCU_CR0_TEMPERATURE_TARGET 0xe4 -#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 -#define PCU_CR0_CURRENT_CONFIG 0xf8 -#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ -#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT) +#define PCU_CR0_FUN 0 +#define PCU_CR0_PLATFORM_INFO 0xa8 +#define PCU_CR0_P_STATE_LIMITS 0xd8 +#define P_STATE_LIMITS_LOCK_SHIFT 31 +#define P_STATE_LIMITS_LOCK (1 << P_STATE_LIMITS_LOCK_SHIFT) +#define PCU_CR0_TEMPERATURE_TARGET 0xe4 +#define PCU_CR0_PACKAGE_RAPL_LIMIT 0xe8 +#define PCU_CR0_CURRENT_CONFIG 0xf8 +#define MAX_NON_TURBO_LIM_RATIO_SHIFT 8 /* 8:15 */ +#define MAX_NON_TURBO_LIM_RATIO_MASK (0xff << MAX_NON_TURBO_LIM_RATIO_SHIFT)
-#define PCU_CR1_BIOS_MB_DATA_REG 0x8c +#define PCU_CR1_BIOS_MB_DATA_REG 0x8c
-#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK BIT(31) -#define BIOS_MB_CMD_MASK 0xff -#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 -#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 -#define BIOS_ERR_INVALID_CMD 0x01 +#define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff +#define BIOS_CMD_READ_PCU_MISC_CFG 0x5 +#define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 +#define BIOS_ERR_INVALID_CMD 0x1
-#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK BIT(1) -#define RST_CPL2_MASK BIT(2) -#define RST_CPL3_MASK BIT(3) -#define RST_CPL4_MASK BIT(4) -#define PCODE_INIT_DONE1_MASK BIT(9) -#define PCODE_INIT_DONE2_MASK BIT(10) -#define PCODE_INIT_DONE3_MASK BIT(11) -#define PCODE_INIT_DONE4_MASK BIT(12) +#define PCU_CR1_BIOS_RESET_CPL_REG 0x94 +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12)
-#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) +#define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31)
#define UBOX_DECS_BUS 0 #define UBOX_DECS_DEV 8 @@ -89,49 +89,49 @@ #define VTD_MMIOL_CSR 0xdc #define VTD_ME_BASE_CSR 0xf0 #define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C +#define VTD_VERSION 0 +#define VTD_CAP 0x8 +#define VTD_CAP_LOW 0x8 +#define VTD_CAP_HIGH 0xC #define VTD_EXT_CAP_HIGH 0x14 #define VTD_LTDPR 0x290
-#define PCU_CR1_C2C3TT_REG 0xdc -#define PCU_CR1_PCIE_ILTR_OVRD 0xfc -#define PCU_CR1_SAPMCTL 0xb0 -#define SAPMCTL_LOCK_SHIFT 31 -#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT) -#define PCU_CR1_MC_BIOS_REQ 0x98 +#define PCU_CR1_C2C3TT_REG 0xdc +#define PCU_CR1_PCIE_ILTR_OVRD 0xfc +#define PCU_CR1_SAPMCTL 0xb0 +#define SAPMCTL_LOCK_SHIFT 31 +#define SAPMCTL_LOCK_MASK (1 << SAPMCTL_LOCK_SHIFT) +#define PCU_CR1_MC_BIOS_REQ 0x98
-#define PCU_CR2_FUN 2 -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c -#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ -#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 -#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ -#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc -#define UNCORE_PLIMIT_OVERRIDE_BIT 20 -#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) -#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 -#define PROCHOT_RATIO 0xa /* bits 0:7 */ +#define PCU_CR2_FUN 2 +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK 0x8c +#define PCIE_IN_PKGCSTATE_L1_MASK 0xFFFFFF /* 23:0 bits */ +#define PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2 0x90 +#define KTI_IN_PKGCSTATE_L1_MASK 0x7 /* 2:0 bits */ +#define PCU_CR2_DYNAMIC_PERF_POWER_CTL 0xdc +#define UNCORE_PLIMIT_OVERRIDE_BIT 20 +#define UNOCRE_PLIMIT_OVERRIDE_SHIFT (1 << UNCORE_PLIMIT_OVERRIDE_BIT) +#define PCU_CR2_PROCHOT_RESPONSE_RATIO_REG 0xb0 +#define PROCHOT_RATIO 0xa /* bits 0:7 */
-#define CHA_UTIL_ALL_DEV 29 -#define CHA_UTIL_ALL_FUNC 1 -#define CHA_UTIL_ALL_MMCFG_CSR 0xc0 +#define CHA_UTIL_ALL_DEV 29 +#define CHA_UTIL_ALL_FUNC 1 +#define CHA_UTIL_ALL_MMCFG_CSR 0xc0
/* PCH Device info */
-#define XHCI_BUS_NUMBER 0x0 -#define PCH_DEV_SLOT_XHCI 0x14 -#define XHCI_FUNC_NUM 0x0 +#define XHCI_BUS_NUMBER 0 +#define PCH_DEV_SLOT_XHCI 0x14 +#define XHCI_FUNC_NUM 0
-#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 +#define HPET_BUS_NUM 0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0
#define MMAP_VTD_CFG_REG_DEVID 0x2024 #define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 -#define VTD_FUNC_NUM 0x0 +#define VTD_FUNC_NUM 0
#if !defined(__SIMPLE_DEVICE__) #define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) @@ -139,34 +139,34 @@ #define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif
-#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
-#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function -#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB +#define CBDMA_DEV_NUM 0x4 +#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function +#define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB
-#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 +#define VMD_DEV_NUM 0x5 +#define VMD_FUNC_NUM 0x5
-#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x00 +#define APIC_DEV_NUM 0x5 +#define APIC_FUNC_NUM 0
-#define PCH_IOAPIC_BUS_NUMBER 0xF0 -#define PCH_IOAPIC_DEV_NUM 0x1F -#define PCH_IOAPIC_FUNC_NUM 0x00 +#define PCH_IOAPIC_BUS_NUMBER 0xF0 +#define PCH_IOAPIC_DEV_NUM 0x1F +#define PCH_IOAPIC_FUNC_NUM 0
// ========== IOAPIC Definitions for DMAR/ACPI ======== -#define PCH_IOAPIC_ID 0x08 +#define PCH_IOAPIC_ID 0x8
// DMI3 B0D0F0 registers #define DMI3_DEVID 0x2020