Attention is currently required from: Kapil Porwal, Sukumar Ghorai, Tarun Tuli.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email )
Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75814/comment/6825ceec_090138eb : PS1, Line 619: 0
IOE.PMC address extracted from PCI device bdf 0/19/2 bar address; and load at runtime from SSRAM. a) looks this address is not available in coreboot today. b) let me check how BIOS configure this IOE-PMC disable ACPI timer NOTE: use itp debugger to verify the IOE/SOC PMC ACPI timer settings.
if we could get the offset and register bit definition. I can give a try and share an image with you.
Looking inside the FSP code, i don't see anything other than SOC.PMC register being programmed under that UPD
now i understood how this programming is getting handled between SOC.PMC and IOE.PMC.
I will share a CL with you sooner,
can you please try this cl: https://review.coreboot.org/c/coreboot/+/75822
w/o this cl:
iotools mmio_read32 0xfe4018fc
0x0
w this cl:
iotools mmio_read32 0xfe4018fc
0x2