Attention is currently required from: Sean Rhodes, Nico Huber, Matt DeVillier, Paul Fagerburg, Angel Pons, Andrey Petrov.
Hello build bot (Jenkins), Sean Rhodes, Nico Huber, Matt DeVillier, Paul Fagerburg, Angel Pons, Andrey Petrov,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/67285
to review the following change.
Change subject: Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown" ......................................................................
Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"
This reverts commit 7ef5376123d4d0ebb811795fcee1de7066f65a0f.
Reason for revert: It was merged before its dependencies so now master is broken.
Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/67285/1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 5bee9bf..da2d00a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,7 +16,6 @@ #include <intelblocks/p2sb.h> #include <intelblocks/power_limit.h> #include <intelblocks/xdci.h> -#include <intelpch/lockdown.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -698,13 +697,11 @@
silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
- /* coreboot handles the lockdown */ - silconfig->LockDownGlobalSmi = 0; - silconfig->BiosLock = 0; - silconfig->BiosInterface = 0; - silconfig->WriteProtectionEnable[0] = 0; - silconfig->SpiEiss = 0; - silconfig->RtcLock = 0; + /* Disable setting of EISS bit in FSP. */ + silconfig->SpiEiss = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + silconfig->RtcLock = 0;
/* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;