[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stage

[Karthik Ramasubramanian (Code Review)]

Hello Karthikeyan Ramasubramanian,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/30074

to review the following change.

Change subject: soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stage
......................................................................

soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stage

Print ME version on exit of BS_DEV_INIT stage so that the HECI device
stays in D3 state as configured by FSP.

BRANCH=octopus
BUG=b:120571529
TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that
the device boots to ChromeOS. Ensure that the device enters S0ix
successfully(using suspend_stress_test -c 25).

Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/soc/intel/apollolake/cse.c
1 file changed, 2 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30074/1

diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index 26249bc..d761a6c 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -195,7 +195,7 @@
    return reg;
 }

-static void dump_cse_version(void)
+static void dump_cse_version(void *unused)
 {
    int res;
    size_t reply_size;
@@ -282,8 +282,6 @@
    	printk(BIOS_DEBUG, "unknown");
    }
    printk(BIOS_DEBUG, "\n");
-
-	dump_cse_version();
 }

#define PCR_PSFX_T0_SHDW_PCIEN		0x1C
@@ -307,3 +305,4 @@
 }

BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, dump_cse_version, NULL);