[coreboot-gerrit] Change in ...coreboot[master]: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33382

Change subject: [WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue
......................................................................

[WIP] mb/google/{sarien, arcada} Fix for SSD can't be detected issue

In order to fix,SSD can't be detected during cold-reset issue, add
the required delays between powering the SSD and resetting it for
cold and warm reboot cases.

BUG=b:132393441
TEST=Boot to OS with cold-reset

Change-Id: I03dabe1f75c761617c1129547342dff3047e101d
Signed-off-by: Bora Guvendik 
---
M src/mainboard/google/sarien/ramstage.c
M src/mainboard/google/sarien/romstage.c
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
4 files changed, 30 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33382/1

diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index 1d22046..2ca6dfb 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -14,7 +14,9 @@
  */

#include <arch/acpi.h>
+#include <bootstate.h>
 #include <drivers/vpd/vpd.h>
+#include <gpio.h>
 #include <smbios.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
@@ -77,3 +79,10 @@
 struct chip_operations mainboard_ops = {
    .enable_dev = mainboard_enable,
 };
+
+static void ssd_reset(void* unused)
+{
+	gpio_set(GPP_H12, 1);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ssd_reset, NULL);
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index 20eee7f..7b6c96f 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -13,9 +13,13 @@
  * GNU General Public License for more details.
  */

+#include <delay.h>
 #include <ec/google/wilco/romstage.h>
 #include <soc/cnl_memcfg_init.h>
+#include <soc/pm.h>
 #include <soc/romstage.h>
+#include <intelblocks/pmclib.h>
+#include <gpio.h>

static const struct cnl_mb_cfg memcfg = {
    /* Access memory info through SMBUS. */
@@ -57,6 +61,19 @@

void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	struct chipset_power_state *ps = pmc_get_power_state();
+
+	if(ps) {
+		if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR)) {
+			gpio_set(GPP_H13, 0);
+			mdelay(75);
+			gpio_set(GPP_H13, 1);
+		}
+		else {
+			gpio_set(GPP_H12, 1);
+		}
+	}
+
    wilco_ec_romstage_init();

cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index ff0240c..a0d21b4 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -16,6 +16,7 @@
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

+
 /* Pad configuration in ramstage */
 static const struct pad_config gpio_table[] = {
 /* RCIN# */		PAD_NC(GPP_A0, NONE),
@@ -240,7 +241,6 @@
 static const struct pad_config early_gpio_table[] = {
 /* M2_SKT2_CFG1 */	PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
 /* SSD RESET pin will stay low first */
-/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
 /* I2C4_SDA */		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
@@ -252,7 +252,7 @@
 /* CPU_GP0 */		PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
-/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
+/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
 };

const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 78db12e..80d68d4 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -229,7 +229,7 @@
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
 /* SSD RESET pin will stay low first */
-/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
+/* M2_SKT2_CFG0 */	//PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
 /* I2C4_SDA */		PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
 /* I2C4_SCL */		PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 /* DMIC_DATA1 */	PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
@@ -240,7 +240,7 @@
 /* SATALED# */		PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 /* DDPD_HPD2 */		PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
 /* PWRBTN# */		PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */
-/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
+/* M2_SKT2_CFG0 */	PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
 };

const struct pad_config *variant_gpio_table(size_t *num)