[coreboot-gerrit] Change in coreboot[master]: mb/google/brya/var/felwinter: Disable PCIE port 6

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59243 )

Change subject: mb/google/brya/var/felwinter: Disable PCIE port 6
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mb/google/brya/var/felwinter: Disable PCIE port 6

PCIE port 6 is empty as per schematics.

BUG=b:206047996
TEST=PCIE port 6 is disabled.

Signed-off-by: Eric Lai 
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index dedd192..5b90b9a 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -60,6 +60,7 @@
    			end
    		end
    	end
+		device ref pcie_rp6 off end
    	device ref pcie_rp8 on
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.