Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45340 )
Change subject: soc/amd/picasso: Generate ACPI pstate and cstate objects in cb ......................................................................
Patch Set 25: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/45340/24/src/include/cpu/amd/msr.h File src/include/cpu/amd/msr.h:
https://review.coreboot.org/c/coreboot/+/45340/24/src/include/cpu/amd/msr.h@... PS24, Line 36: #define PS_LIM_MAX_VAL_MASK (0x7 << PS_MAX_VAL_SHFT) : #define MAX_PSTATES 8
This MSR is consistent between family 15h and 17h for these fields, so i left these here intentional […]
But it doesn't look like it's applicable to all AMD families. We can leave it here, but we might have to move this to SoC eventually at some point.
https://review.coreboot.org/c/coreboot/+/45340/24/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45340/24/src/soc/amd/picasso/acpi.c... PS24, Line 379: cstate_info[1].resource.addrl = : (rdmsr(MSR_CSTATE_ADDRESS).lo & MSR_CSTATE_ADDRESS_MASK) + 1;
Done
SG