Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Anjaneya "Reddy" Chagam, Damien Zammit, Lee Leahy, Marshall Dawson, Johnny Lin, Christian Walter, Suresh Bellampalli, Vanessa Eusebio, Tim Chu, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63594 )
Change subject: arch/x86/postcar_loader.c: Add common code for CBMEM and TSEG ......................................................................
arch/x86/postcar_loader.c: Add common code for CBMEM and TSEG
Move the boilerplate code to set up MTRR for cbmem and TSEG into a common location.
The empty function calls will be cleaned up in a follow up.
Change-Id: I86c76c69fdb6a7930c2ba7dcd21fd9d368c680e0 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/postcar_loader.c M src/drivers/intel/fsp1_1/car.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/xeon_sp/memmap.c 17 files changed, 36 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63594/1
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 810be93..0545210 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -10,6 +10,7 @@ #include <reset.h> #include <rmodule.h> #include <stage_cache.h> +#include <stdint.h> #include <timestamp.h> #include <security/vboot/vboot_common.h>
@@ -48,11 +49,45 @@ postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type); }
+static void postcar_frame_add_cbmem_cache(struct postcar_frame *pcf) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + + /* Try account for the CBMEM region currently used and for future use */ + cbmem_get_region((void **)&cbmem_base, &cbmem_size); + + if (cbmem_base <= 4 * MiB) + return; + cbmem_base -= 4 * MiB; + cbmem_size += 4 * MiB; + /* Align to make sure we don't use too many MTRR's */ + cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); + cbmem_size = ALIGN_UP(cbmem_size, 4 * MiB); + + postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); +} + +static void postcar_frame_add_external_stage_cache(struct postcar_frame *pcf) +{ + if (CONFIG(TSEG_STAGE_CACHE)) + return; + uintptr_t stage_cache_base; + size_t stage_cache_size; + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + if (stage_cache_size != 0) + postcar_frame_add_mtrr(pcf, stage_cache_base, stage_cache_size, MTRR_TYPE_WRBACK); +} + static void postcar_frame_common_mtrrs(struct postcar_frame *pcf) { if (pcf->skip_common_mtrr) return;
+ postcar_frame_add_cbmem_cache(pcf); + + postcar_frame_add_external_stage_cache(pcf); + /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 5d41a01..65cf3d4 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -12,14 +12,6 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); - }
/* This is the romstage entry called from cpu/intel/car/romstage.c */ diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index 75ab352..5a2aa6b 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -62,4 +62,5 @@ /* Nothing to do, MTRRs are no-op on QEMU. */ void fill_postcar_frame(struct postcar_frame *pcf) { + pcf->skip_common_mtrr = 1; } diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 28edb38..2e98cf0 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -118,15 +118,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - } diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index c19cfec..84fe86f 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -69,12 +69,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..321421c 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -53,11 +53,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - } diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1dea21c..556b9a7 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -83,13 +83,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 78fbae8..de34a38 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -35,13 +35,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index c02cf35..fa1c873 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -87,14 +87,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* - * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both - * CBMEM and the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), - MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index f667544..0df49ed 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -67,22 +67,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - - /* - * Cache 8MiB below the top of ram. On sandybridge systems the top of - * RAM under 4GiB is the start of the TSEG region. It is required to - * be 8MiB aligned. Set this area as cacheable so it can be used later - * for ramstage before setting up the entire RAM as cacheable. - */ - postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); - - /* - * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems - * is where the TSEG region resides. However, it is not restricted - * to SMM mode until SMM has been relocated. By setting the region - * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. - */ - postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index dced902..f942c09 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -85,14 +85,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of - * RAM to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); } diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index b7731b0..f78d2f0 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -125,11 +125,6 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); }
void SetMemParams(AMD_POST_PARAMS *PostParams) diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..5987e0b 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,13 +29,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index b467dc0..f0d7b76 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -47,13 +47,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index a67d050..0988f14 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -68,22 +68,6 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ - uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); - - /* - * We need to make sure ramstage will be run cached. At this - * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs below cbmem top which is - * a safe bet to cover ramstage. - */ - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); - /* Cache the extended BIOS region if it is supported */ fast_spi_cache_ext_bios_postcar(pcf); } diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f607d0f..c417ee1 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -41,17 +41,4 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache the TSEG region */ - postcar_enable_tseg_cache(pcf); } diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index b640c2d..2586e7e 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -29,25 +29,6 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - uintptr_t cbmem_base; - size_t cbmem_size; - - /* Try account for the CBMEM region currently used and for future use */ - cbmem_get_region((void **)&cbmem_base, &cbmem_size); - printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); - /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ - cbmem_base -= 4 * MiB; - cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); - - /* Align the top to make sure we don't use too many MTRR's */ - cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB); - - postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); - /* Cache the TSEG region */ - if (CONFIG(TSEG_STAGE_CACHE)) - postcar_enable_tseg_cache(pcf); }
#if !defined(__SIMPLE_DEVICE__)