Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47531 )
Change subject: soc/intel/common/block/p2sb: Add hpet BDF functions ......................................................................
soc/intel/common/block/p2sb: Add hpet BDF functions
This allows to get/set the HPET bus device function.
Change-Id: I8d72da8bc392aa144d167d31cde30cc71cd1396e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/p2sb.c 2 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47531/1
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 71f9c62..7cf0c48 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -29,6 +29,18 @@ void p2sb_enable_bar(void); void p2sb_configure_hpet(void);
+union p2sb_bdf { + uint16_t raw; + struct { + uint16_t fn : 3; + uint16_t dev : 5; + uint16_t bus : 8; + }; +}; + +union p2sb_bdf p2sb_get_hpet_bdf(void); +void p2sb_set_hpet_bdf(union p2sb_bdf bdf); + /* SOC overrides */ /* * Each SoC should implement EP Mask register to disable SB access diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index b5f9a07..93f711f 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -56,6 +56,22 @@ pci_write_config8(PCH_DEV_P2SB, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); }
+union p2sb_bdf p2sb_get_hpet_bdf(void) +{ + union p2sb_bdf bdf; + bool p2sb_state = p2sb_is_hiden(); + p2sb_unhide(); + bdf.raw = pci_read_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF); + if (p2sb_state) + p2sb_hide(); + return bdf; +} + +void p2sb_set_hpet_bdf(union p2sb_bdf bdf) +{ + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, bdf.raw); +} + static void p2sb_set_hide_bit(int hide) { const uint16_t reg = PCH_P2SB_E0 + 1;