Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email )
Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ......................................................................
soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
On Panther Lake, the Thunderbolt port index exposed by the LCAP registers now begins at 0x15.
The previous offset of 0x10 caused an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the port
This error led to instability in PCIe tunneling during power state transitions.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/1
diff --git a/src/soc/intel/pantherlake/pcie_rp.c b/src/soc/intel/pantherlake/pcie_rp.c index 1b302fd..7c51601 100644 --- a/src/soc/intel/pantherlake/pcie_rp.c +++ b/src/soc/intel/pantherlake/pcie_rp.c @@ -5,13 +5,13 @@ #include <soc/pcie.h>
/* - * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe - * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's + * TBT's LCAP registers are returning port index which starts from 0x15 (Usually for other PCIe + * root ports index starts from 1). Thus keeping lcap_port_base 0x15 for TBT, so that coreboot's * PCIe remapping logic can return correct index (0-based) */
static const struct pcie_rp_group tbt_rp_groups[] = { - { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x15 }, { 0 } };