[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/tsc: fix clock divisor range check

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48287 )

Change subject: soc/amd/picasso/tsc: fix clock divisor range check
......................................................................

soc/amd/picasso/tsc: fix clock divisor range check

The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.

TEST=Compared with Picasso's PPR #55570

Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held 
---
M src/soc/amd/picasso/tsc_freq.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/48287/1

diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c
index 8a541fc..55c8665 100644
--- a/src/soc/amd/picasso/tsc_freq.c
+++ b/src/soc/amd/picasso/tsc_freq.c
@@ -33,7 +33,7 @@
    if (!cpudid) {
    	mhz = TSC_DEFAULT_FREQ_MHZ;
    	printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz);
-	} else if ((cpudid >= 8) && (cpudid < 0x3c)) {
+	} else if ((cpudid >= 8) && (cpudid <= 0x30)) {
    	mhz = (200 * cpufid) / cpudid;
    } else {
    	mhz = 25 * cpufid;