[coreboot-gerrit] Change in coreboot[master]: mainboard/google/puff: Enable pcie7 ep in dt

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37804 )

Change subject: mainboard/google/puff: Enable pcie7 ep in dt
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mainboard/google/puff: Enable pcie7 ep in dt

Missing bus init for RTL8111H ethernet chip hanging on bus.

BRANCH=none
BUG=b:146437819
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I22aba312f183ea05eeb81d326ca0c05ce340a2e8
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/37804/1

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 22e10c5..9ef39a6 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -59,6 +59,7 @@
    register "sdcard_cd_gpio" = "vSD3_CD_B"

device domain 0 on
+		device pci 07.0 on end # RTL8111H NIC.
    	device pci 15.0 off
    		# RFU - Reserved for Future Use.
    	end # I2C #0