Change subject: soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform
......................................................................
I know this isn't added in this change, but shouldn't VtdItbtEnable be set based on whether mainboar […]
--
To view, visit
https://review.coreboot.org/c/coreboot/+/43657
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Gerrit-Change-Number: 43657
Gerrit-PatchSet: 4
Gerrit-Owner: John Zhao
john.zhao@intel.com
Gerrit-Reviewer: Divya S Sasidharan
divya.s.sasidharan@intel.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Lalithambika Krishnakumar
lalithambika.krishnakumar@intel.corp-partner.google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Rajat Jain
rajatja@google.com
Gerrit-Reviewer: Shamile Khan
shamile.khan@intel.com
Gerrit-Reviewer: Wonkyu Kim
wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Paul Menzel
paulepanter@users.sourceforge.net
Gerrit-Comment-Date: Wed, 22 Jul 2020 17:51:01 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Furquan Shaikh
furquan@google.com
Gerrit-MessageType: comment