[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Preload dsdt.aml

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59505 )

Change subject: soc/amd/cezanne: Preload dsdt.aml
......................................................................

soc/amd/cezanne: Preload dsdt.aml

This will save about 2ms.

BUG=b:179699789
TEST=Boot guybrush and verify reduction in boot time.
| 80 - write tables                                   | 1.08      | 1.37      Δ(  0.29,    0.02%) |
| 85 - finalize chips                                 | 15.575    | 13.164    Δ( -2.41,   -0.17%) |

Signed-off-by: Raul E Rangel 
Change-Id: I6b268eba7b8c60dcf9d3b366b27b51a1c83a3c00
---
M src/soc/amd/cezanne/preload.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/59505/1

diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
index e713912..43da4b6 100644
--- a/src/soc/amd/cezanne/preload.c
+++ b/src/soc/amd/cezanne/preload.c
@@ -18,6 +18,7 @@
  */
 static void start_post_elog_preloads(void *unused)
 {
+	preload_acpi_dsdt();
    if (!acpi_is_wakeup_s3())
    	payload_preload();
 }