Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13696
-gerrit
commit 29af6c8133b4b3f4d830483b4ce54bcbf0d8025d Author: Duncan Laurie dlaurie@chromium.org Date: Tue Feb 9 09:21:41 2016 -0800
skylake: Check for power failure when WAK_STS is not set
The PCH does not set PM1_STS[WAK_STS] bit when waking from a G3 state, which is triggered by hiberante now on chell when we do a PMIC shutdown. This means the checks for S5 wake are not done and instead it is logged as a wake from S0.
BUG=chrome-os-partner:50076 BRANCH=glados TEST=pass firmware_EventLog test on chell
Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783 Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382 Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/326888 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/skylake/romstage/power_state.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c index 1987534..85234b5 100644 --- a/src/soc/intel/skylake/romstage/power_state.c +++ b/src/soc/intel/skylake/romstage/power_state.c @@ -69,6 +69,14 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps) } /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } else { + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = SLEEP_STATE_S5; }
/*