[coreboot-gerrit] Change in coreboot[master]: mb/purism/librem_skl: Relocate devicetree FSP settings

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43890 )

Change subject: mb/purism/librem_skl: Relocate devicetree FSP settings
......................................................................

mb/purism/librem_skl: Relocate devicetree FSP settings

Tested with BUILD_TIMELESS=1, Librem 15 v4 does not change.

Change-Id: Ia968c7ab0b7b305c0c32f43eafc4d25d670a135e
Signed-off-by: Angel Pons 
---
M src/mainboard/purism/librem_skl/devicetree.cb
1 file changed, 48 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/43890/1

diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 51f6ba4..81f2e31 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -45,29 +45,12 @@

# FSP Configuration
    register "ProbelessTrace" = "0"
-	register "EnableLan" = "0"
-	register "EnableSata" = "1"
-	register "SataSalpSupport" = "0"
-	register "SataMode" = "0"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "0"
-	register "SataPortsEnable[2]" = "1"
-	register "SataPortsDevSlp[0]" = "0"
-	register "SataPortsDevSlp[2]" = "0"
-	register "EnableAzalia" = "1"
    register "DspEnable" = "0"
    register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
    register "SsicPortEnable" = "0"
-	register "SmbusEnable" = "1"
    register "Cio2Enable" = "0"
-	register "ScsEmmcEnabled" = "0"
-	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
-	register "Device4Enable" = "1"
-	register "HeciEnabled" = "0"
    register "SaGv" = "3"
    register "PmConfigSlpS3MinAssert" = "2"		# 50ms
    register "PmConfigSlpS4MinAssert" = "1"		# 1s
@@ -154,10 +137,6 @@
    	.dc_loadline = 420,
    }"

-	# Enable Root Ports 5 and 9
-	register "PcieRpEnable[4]" = "1"
-	register "PcieRpEnable[8]" = "1"
-
    # PL2 override 25W
    register "power_limits_config" = "{
    	.tdp_pl2_override = 25,
@@ -177,27 +156,60 @@
    device domain 0 on
    	device pci 00.0 on  end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device
+
+		# FIXME: corresponding device entry is missing
+		register "Device4Enable" = "1"
+
    	device pci 14.0 on  end # USB xHCI
    	device pci 14.1 on  end # USB xDCI (OTG)
    	device pci 14.2 on  end # Thermal Subsystem
-		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.0 on      # Management Engine Interface 1
+
+			# FIXME: does not match devicetree!
+			register "HeciEnabled" = "0"
+		end
    	device pci 16.1 off end # Management Engine Interface 2
    	device pci 16.2 off end # Management Engine IDE-R
    	device pci 16.3 off end # Management Engine KT Redirection
    	device pci 16.4 off end # Management Engine Interface 3
-		device pci 17.0 on  end # SATA
+		device pci 17.0 on      # SATA
+			register "EnableSata" = "1"
+			register "SataSalpSupport" = "0"
+			register "SataMode" = "0"
+
+			register "SataPortsEnable" = "{ \
+				[0]	= 1, \
+				[2]	= 1, \
+			}"
+			register "SataPortsDevSlp" = "{ \
+				[0]	= 0, \
+				[2]	= 0, \
+			}"
+		end
    	device pci 1c.0 on  end # PCI Express Port 1
    	device pci 1c.1 off end # PCI Express Port 2
    	device pci 1c.2 off end # PCI Express Port 3
    	device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.4 off     # PCI Express Port 5
+
+			# FIXME: Maybe it's due to FSP coalescing?
+			register "PcieRpEnable[4]" = "1"
+		end
    	device pci 1c.5 off end # PCI Express Port 6
    	device pci 1c.6 off end # PCI Express Port 7
    	device pci 1c.7 off end # PCI Express Port 8
-		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.0 on      # PCI Express Port 9
+			register "PcieRpEnable[8]" = "1"
+		end
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
+
+		# eMMC/SD are disabled
+		register "ScsEmmcEnabled" = "0"
+		register "ScsEmmcHs400Enabled" = "0"
+		register "ScsSdCardEnabled" = "0"
+
    	device pci 1f.0 on
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end
@@ -205,9 +217,17 @@
    	end # LPC Interface
    	device pci 1f.1 on  end # P2SB
    	device pci 1f.2 on  end # Power Management Controller
-		device pci 1f.3 on  end # Intel HDA
-		device pci 1f.4 on  end # SMBus
+		device pci 1f.3 on      # Intel HDA
+			register "EnableAzalia" = "1"
+		end
+		device pci 1f.4 on      # SMBus
+			register "SmbusEnable" = "1"
+		end
    	device pci 1f.5 on  end # PCH SPI
-		device pci 1f.6 off end # GbE
+		device pci 1f.6 off     # GbE
+			register "EnableLan" = "0"
+		end
+
+		register "EnableTraceHub" = "0"
    end
 end