Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4889
-gerrit
commit 3ea5887ffd2d40687f8276e2afb3859d0ec12d13 Author: Aaron Durbin adurbin@chromium.org Date: Mon Oct 21 12:36:17 2013 -0500
baytrail: bring up APs
Bring up the APs using x86 MP infrastructure.
BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi. Noted all cores are brought up.
Change-Id: I9231eff5494444e8eb17ecdc5a0af72a2e5208b5 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/173704 --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 7 +-- src/soc/intel/baytrail/cpu.c | 82 ++++++++++++++++++++++++++++++ 5 files changed, 86 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 048e783..c4585fb 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES + select PARALLEL_MP select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 2cae746..fc6414c 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -22,6 +22,7 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += reset.c ramstage-y += reset.c +ramstage-y += cpu.c
# Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index ff0397c..790b8c6 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -25,6 +25,7 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); +void baytrail_init_cpus(device_t dev); void set_max_freq(void);
extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 5a898f6..0f686fa 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -40,18 +40,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) -{ - printk(BIOS_DEBUG, "cpu_bus_init()\n"); -} - static void cpu_bus_noop(device_t dev) { }
static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, + .init = baytrail_init_cpus, .scan_bus = NULL, };
diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c new file mode 100644 index 0000000..4217947 --- /dev/null +++ b/src/soc/intel/baytrail/cpu.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/mp.h> + +#include <baytrail/pattrs.h> +#include <baytrail/ramstage.h> + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), +}; + +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + const struct pattrs *pattrs = pattrs_get(); + struct mp_params mp_params; + + /* Set up MTRRs based on physical address size. */ + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_mtrr_check(); + + mp_params.num_cpus = pattrs->num_cpus, + mp_params.parallel_microcode_load = 1, + mp_params.adjust_apic_id = adjust_apic_id; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = intel_microcode_find(); + mp_params.microcode_pointer = NULL; + + if (mp_init(cpu_bus, &mp_params)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } +} + +static void baytrail_core_init(device_t cpu) +{ + printk(BIOS_DEBUG, "Init BayTrail core.\n"); +} + +static struct device_operations cpu_dev_ops = { + .init = baytrail_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x30673 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; +