Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31420 )
Change subject: SMBIOS: Update Processor Information structure to v3.2.0 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/31420/7/src/arch/x86/smbios.c File src/arch/x86/smbios.c:
https://review.coreboot.org/#/c/31420/7/src/arch/x86/smbios.c@564 PS7, Line 564: (res.ebx >> 16) & 0xff;
by my understanding, that is "core_enabled". […]
Elyes, there are two levels of disablement, what the silicon vendor can disable and what the firmware can disable. SMBios spec won't account for the former.
My interpretation:
* x – maximum number of cores that are physically present * n – maximum number of cores that silicon vendor allows us to use * e – number of active cores
What CPUID (leaf 1 as currently used, or 4 as you described*) reports might be `x`. SMBios `core_count` would be `n` and `core_enabled` `e`. Also, to make it more confusing, whenever Intel writes `cores` it could mean logical cores, in SMBios: threads :-/ Especially, when IDs are mentioned, because each logical core has its own ID.
*Both CPUID 1 EBX[23:16] and CPUID 4 EAX[31:26] have the same description in the current SDM "Maximum number of addressable IDs for processor cores in the physical package".