Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 )
Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/voltee... PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped.
+Furquan for details, but I believe you cannot do this due to the issue described in this comment. […]
That is correct, x86 only memory maps the top 16 MiB of SPI flash, so in this case RW_SECTION_A ends up at 0x1000000 (16 MiB) up from the bottom of flash, so aligns at the 16MiB boundary and all FW will be memory mapped. Somehow all of the FW has to live up beyond that boundary. I think removing 2MB from each FW_MAIN may work, as we are only using ~1.6MiB from each section, out of the ~5.8. However, that puts us perilously close to not being able to fit a cse lite update in the FW_MAIN regions...