[coreboot-gerrit] [S] Change in coreboot[master]: [HACK]soc/apl: Get 64 bit mode working

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68170 )

Change subject: [HACK]soc/apl: Get 64 bit mode working
......................................................................

[HACK]soc/apl: Get 64 bit mode working

This also needs UPD headers fixed (simply 's/VOID */UINT32/')

TESTED on up/squared.

Change-Id: Ib827df1213fab8c85c38f3029c860dc4d36165fd
Signed-off-by: Arthur Heymans 
---
M src/cpu/x86/mp_init.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/Makefile.inc
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/common/block/xhci/xhci.c
5 files changed, 21 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68170/1

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index df74d24..16654bc 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -496,7 +496,7 @@
     * resources such as UART, so scale the time out up by increments of
     * 100ms if needed.
     */
-	const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus);
+	const int timeout_us = 10000000;
    const int step_us = 100;
    int num_aps = mp_params->num_cpus - 1;
    struct stopwatch sw;
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index b2c2246..f849087 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -25,6 +25,7 @@
    select ACPI_INTEL_HARDWARE_SLEEP_VALUES
    select ACPI_NO_PCAT_8259
    select ARCH_X86
+	select HAVE_EXP_X86_64_SUPPORT
    select BOOT_DEVICE_SUPPORTS_WRITES
    # CPU specific options
    select CPU_INTEL_COMMON
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 8f36d4b..0df2cd7 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -203,4 +203,6 @@
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*)
 endif

+CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0x1000:$(call int-subtract, 0x100000000 0xefe000):0xefe000
+
 endif # if CONFIG_SOC_INTEL_APOLLOLAKE
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 757bad3..4d7f893 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -27,6 +27,7 @@
 #include <soc/romstage.h>
 #include <soc/systemagent.h>
 #include <spi_flash.h>
+#include <stdint.h>
 #include <timer.h>
 #include "chip.h"

@@ -317,7 +318,7 @@
     */

mupd->FspmConfig.VariableNvsBufferPtr =
-		mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version,
+		(uint32_t)(uintptr_t)mrc_cache_current_mmap_leak(MRC_VARIABLE_DATA, version,
    				    NULL);

assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 4a40834..07dc7d3 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -21,7 +21,7 @@

static uint8_t *xhci_mem_base(void)
 {
-	uint32_t mem_base = pci_read_config32(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0);
+	uintptr_t mem_base = pci_read_config32(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0);

/* Check if the controller is disabled or not present */
    if (mem_base == 0 || mem_base == 0xffffffff)