John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42954 )
Change subject: mb/intel/tglrvp: Enable s0ix for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Enable s0ix for tglrvp_up3
This change enables s0ix for tglrvp_up3 platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/42954/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..492054d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -113,6 +113,9 @@ register "TcssXhciEn" = "1" register "TcssAuxOri" = "0"
+ # Enable S0ix + register "s0ix_enable" = "1" + # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1"