Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee.
Hello Derek Huang, Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68806
to look at the new patch set (#3).
Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave ......................................................................
mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4.
BUG=b:249000573 BRANCH=brask TEST=emerge-brask coreboot
Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8 Signed-off-by: Raymond Chung raymondchung@ami.corp-partner.google.com --- A src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/memory.c 2 files changed, 64 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/68806/3