[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
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mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2

The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.

BUG=b:374205496
TEST=Boot to OS and then check link speed.
     Use command: lspci -vv | grep 'LnkSta'

Before
     LnkSta: Speed 8GT/s (downgraded), Width x1
     After
     LnkSta: Speed 5GT/s (downgraded), Width x1

Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85520
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb
index 9f62d27..136bf1c 100644
--- a/src/mainboard/google/brya/variants/riven/overridetree.cb
+++ b/src/mainboard/google/brya/variants/riven/overridetree.cb
@@ -487,6 +487,7 @@
    			.clk_src = 2,
    			.clk_req = 2,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_pcie_speed = SPEED_GEN2,
    		}"
    		chip drivers/wifi/generic
    			register "wake" = "GPE0_DW1_03"