[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 )

Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/63630/comment/c6935977_d9092c9a 
PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set.
> Could you please test what happens after setting the WPD bit from the OS? For example, using setpci:
>
> sudo setpci -s 0:1f.0 0xdc.b=0x0a
>
> I ask because I had troubles with the SPI PCI device where the SMI handler would fail to clear the SMI source, and the system would hang (it would be stuck in a SMI storm). See CB:50754 for the fix. I don't think this issue can happen with LPC, but I'd appreciate if you could test just to make sure.

I don't see any problem while running `setpci` from OS as requested.