[coreboot-gerrit] Change in coreboot[master]: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44890 )

Change subject: mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree
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mb/google/zork/trembyle: move PCIe GPP clock setting to devicetree

BUG=b:149970243
BRANCH=zork

Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0
Signed-off-by: Felix Held 
---
M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
2 files changed, 9 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44890/1

diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 62395a1..46ca699 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -180,6 +180,15 @@

register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"

+	# genral purpose PCIe clock output configuration
+	register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN
+	register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader
+	register "gpp_clk_config[2]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[3]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD
+	register "gpp_clk_config[5]" = "GPP_CLK_OFF"
+	register "gpp_clk_config[6]" = "GPP_CLK_OFF"
+
    device cpu_cluster 0 on
    	device lapic 0 on end
    end
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
index 49d8ade..7ce78d9 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
@@ -31,7 +31,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ4,
    },
    {
    	// WLAN
@@ -45,7 +44,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0,
    },
    {
    	// SD Reader
@@ -59,7 +57,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1,
    }
 };

@@ -76,7 +73,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ4,
    },
    {
    	// WLAN
@@ -90,7 +86,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ0,
    },
    {
    	// SD Reader
@@ -104,7 +99,6 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = CLK_REQ1,
    }
 };