[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/brox/jubilant: Update GPE0 routing

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Nick Vaccaro, Ren Kuo, Subrata Banik.

Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84124?usp=email )

Change subject: mb/google/brox/jubilant: Update GPE0 routing
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Patch Set 4:

(1 comment)

File src/mainboard/google/brox/variants/jubilant/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/84124/comment/6f4b4b87_8e5d2b68?usp... :
PS4, Line 25: register "pmc_gpe0_dw1" = "GPP_F"
> if wake sources are scattered across more than 3 GPIO bank then you can use GPIO Tier 1 register to add additional entries.

I am not seeing any precedence for that. Also chip config does not seem to support more than 3 entries. It seems we need to configure PMC as well as GPIO communities for every tier. Should I ask Intel's support on this one?