Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74403 )
Change subject: soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT ......................................................................
soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing something with S3, but it's actually disabling D3Cold support.
Rename it to D3COLD_SUPPORT to make it clear what it's doing.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/starlabs/starbook/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/alderlake/acpi/tcss_dma.asl M src/soc/intel/alderlake/acpi/tcss_pcierp.asl M src/soc/intel/alderlake/acpi/tcss_xhci.asl M src/soc/intel/alderlake/fsp_params.c 8 files changed, 56 insertions(+), 24 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 914ce9f..5761fad 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -11,7 +11,6 @@ select MEMORY_MAPPED_TPM select PCIEXP_SUPPORT_RESIZABLE_BARS select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_ALDERLAKE_S3
if BOARD_PRODRIVE_ATLAS_BASEBOARD
@@ -26,6 +25,9 @@ and therefore not always required. default n
+config D3COLD_SUPPORT + default n + config MAINBOARD_FAMILY string default "PRODRIVE_ATLAS_SERIES" diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 3b55a86..17be0a2 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -62,7 +62,6 @@ select MEMORY_MAPPED_TPM select SOC_INTEL_ALDERLAKE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_ALDERLAKE_S3 select SPI_FLASH_WINBOND select TPM_MEASURED_BOOT select PCIEXP_SUPPORT_RESIZABLE_BARS @@ -84,6 +83,9 @@ config CONSOLE_SERIAL default n if !EDK2_DEBUG
+config D3COLD_SUPPORT + default n + config DEVICETREE default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0913480..9c80054 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -332,11 +332,19 @@ int default 8
-config SOC_INTEL_ALDERLAKE_S3 +config D3COLD_SUPPORT bool - default n + default y help - Select if using S3 instead of S0ix to disable D3Cold. + Enable this option if all devices on your system support the + D3Cold power management state. The D3Cold state is a low-power + state where the device has been powered down and is no longer + able to maintain its context. This state can help reduce + overall system power consumption, which can be beneficial for + energy savings and thermal management. + + Please note that enabling D3Cold support may break system + suspend-to-RAM (S3) functionality.
config ENABLE_SATA_TEST_MODE bool "Enable test mode for SATA margining" diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 1f626fc..5c95997 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -583,7 +583,7 @@ } }
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -654,7 +654,7 @@ STAT = 0 } } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT
/* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 1483c0b..ca47bd0 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,16 +28,16 @@
Method (_S0W, 0x0) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x04) #else Return (0x03) -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
Method (_PR0) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -49,12 +49,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
Method (_PR3) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If (DUID == 0) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -66,7 +66,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
/* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 4f1eec5..6dbde46 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -247,16 +247,16 @@
Method (_S0W, 0x0, NotSerialized) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x4) #else Return (0x3) -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
Method (_PR0) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -268,12 +268,12 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
Method (_PR3) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) If ((TUID == 0) || (TUID == 1)) { Return (Package() { _SB.PCI0.D3C, _SB.PCI0.TBT0 }) } Else { @@ -285,7 +285,7 @@ } Else { Return (Package() { _SB.PCI0.TBT1 }) } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
/* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index c0dc141..ddc5a66 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@
Method (_S0W, 0x0, NotSerialized) { -#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Return (0x4) #else Return (0x3) -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT }
/* @@ -43,7 +43,7 @@ */ Name (SD3C, 0)
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) +#if CONFIG(D3COLD_SUPPORT) Method (_PR0) { Return (Package () { _SB.PCI0.D3C }) @@ -53,7 +53,7 @@ { Return (Package () { _SB.PCI0.D3C }) } -#endif // SOC_INTEL_ALDERLAKE_S3 +#endif // D3COLD_SUPPORT
/* * XHCI controller _DSM method diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 9b360e7..704f910 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -648,7 +648,7 @@
/* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = !CONFIG(SOC_INTEL_ALDERLAKE_S3) && !config->tcss_d3_cold_disable; + s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT) && !config->tcss_d3_cold_disable;
s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {