Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42557 )
Change subject: soc/intel/tigerlake: Disable CPU PCIE in FSP ......................................................................
Patch Set 3:
(5 comments)
a
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@7 PS3, Line 7: PCIE PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@9 PS3, Line 9: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3//COMMIT_MSG@18 PS3, Line 18: this patch.
Fits on the line above?
Tiiight, but it does if split up like this:
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the boot time. FspSilicontInit time is reduced by ~30ms with this patch.
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 207: Pcie PCIe
https://review.coreboot.org/c/coreboot/+/42557/3/src/soc/intel/tigerlake/rom... PS3, Line 208: 0 I would say someone will eventually use the CPU PCie root ports. Could you please expand the comment and mention which PCI devices (Bus:Dev.Function) are controlled by this UPD?