Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Kyösti Mälkki. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61215 )
Change subject: device: Add support for PCIe Resizable BARs ......................................................................
Patch Set 2: Code-Review+1
(5 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/61215/comment/b9cc0656_b163bab0 PS2, Line 656: For instance, if a device requests : 30 bits of address space (1 GiB), but this field is set to 29, then : the device will only be allocated 29 bits worth of address space (512 : MiB). what will be the case when device may request for 28 bits address space (256MB) and default is set to 29 (512MB)? I believe it won't upgrade the bar instead allocate the BAR that device has requested.
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/61215/comment/f2132642_0c1f30e9 PS2, Line 324: ctrl0 can we rename this to rebar_ctrl_reg or ctrl_reg.
Unable to understand why we have '0' here.
https://review.coreboot.org/c/coreboot/+/61215/comment/f21c4d5d_8d7c62b8 PS2, Line 324: const uint32_t ctrl0 = pci_read_config32( : dev, offset + PCI_REBAR_CTRL_OFFSET); nit: I believe it can fit even in single line?
https://review.coreboot.org/c/coreboot/+/61215/comment/1fedcf76_86e7d176 PS2, Line 330: ctrl regbar_cap_reg ?
File src/include/device/pci_def.h:
https://review.coreboot.org/c/coreboot/+/61215/comment/1bf22a10_b2af2144 PS2, Line 535: 0xe0 for easy understanding
nit: (BIT 7 | BIT 6 | BIT 5)