Attention is currently required from: Hung-Te Lin, Paul Menzel.
Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/83923?usp=email )
Change subject: soc/mediatek/mt8196: Add NOR-Flash support ......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83923/comment/90ab93e1_6739f134?usp... : PS5, Line 11: TEST=read nor flash data successfully.
Any benchmark data for the record?
no, there is no benchmark data of nor flash.
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/83923/comment/77a3bbc2_5e8319a2?usp... : PS5, Line 33: void mtk_snfc_init(void) : { : const struct pad_func *ptr; : : for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) { : ptr = &nor_pinmux[i]; : : gpio_set_pull(ptr->gpio, GPIO_PULL_ENABLE, ptr->select); : gpio_set_mode(ptr->gpio, ptr->func); : : if (gpio_set_driving(ptr->gpio, GPIO_DRV_14_MA) < 0) : printk(BIOS_ERR, : "%s: failed to set pin drive to 14 mA for %d\n", : __func__, ptr->gpio.id); : else : printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__, : gpio_get_driving(ptr->gpio)); : } : }
Looks quite similar to the implementation in `src/soc/mediatek/mt8188/spi.c`. […]
There are also differences in GPIO name and number. Do you have any suggestions?