Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83980?usp=email
to look at the new patch set (#3).
Change subject: soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr ......................................................................
soc/intel/common/tcss: Move AUX bias ctrl reg defines to SOC hdr
These field defines are SOC-specific. The AUX bias virtual wire field positons are shifted in PTL.
In MTL SOC and older: 7:0 GROUP_ID Group ID in PCH GPIO 10:8 BIT_NUM Data bit Position in PCH GPIO 23:16 VW_INDEX VW Index in PCH GPIO
In PTL SOC: 15:0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID 18:16 BIT_NUM Data bit Position in PCH GPIO 31:24 VW_INDEX VW Index in PCH GPIO
BUG= TEST=boot to OS and use iotools to read AUX Bias Ctrl register to verify the group ID, bit number, and vw index.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I0f9c895590465b2f539c91834cf331fcd7efa996 --- M src/soc/intel/alderlake/include/soc/tcss.h M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/meteorlake/include/soc/tcss.h M src/soc/intel/tigerlake/include/soc/tcss.h 4 files changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83980/3