[coreboot-gerrit] Change in coreboot[master]: soc/intel/cnl: Add provision to configure SD controller write protect...

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34900 )

Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin
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soc/intel/cnl: Add provision to configure SD controller write protect pin

FSP allows provison to configure SD controller WP pin, however some
of board design might choose not to use the SD WP pin from SD card
controller. This implementation adds a config that allows to enable
/disable SD controller WP pin configuration from FSP.

Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 71aa208..4056817 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -186,6 +186,8 @@
    uint8_t EmmcHs400RxStrobeDll1;
    /* 0-78: number of active delay for TX data, unit is 125 psec */
    uint8_t EmmcHs400TxDataDll;
+	/* Enable/disable SD Card Write Protect Pin */
+	uint8_t ScsSdCardWpPinEnabled;

/* Integrated Sensor */
    uint8_t PchIshEnable;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 0f27c47..612e582 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -336,6 +336,7 @@
    	params->ScsSdCardEnabled = dev->enabled;
    	params->SdCardPowerEnableActiveHigh =
    		CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
+		params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled;
    }

dev = pcidev_path_on_root(PCH_DEVFN_UFS);