[coreboot-gerrit] Change in coreboot[master]: vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI: Overflow before widen

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[e-mail] has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36081 )

Change subject: vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI: Overflow before widen
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vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI: Overflow before widen

Evaluated using 32-bit arithmetic, then used in a context that
expects an expression of type UINT64. Cast to UINT64_t instead.

Change-Id: I4f0aa26e116b47505633897c790ca8e86ea5dc4e
Signed-off-by: Joe Moore 
Found-by: Coverity CID 1241847
---
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36081/1

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
index 856a21a..b842c81 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
@@ -716,7 +716,7 @@
   UINT8 i;

DctMemLimit = 0;
-  if (DctInterleavedMemSize == NBPtr->DCTPtr->Timings.DctMemSize << 6) {
+  if (DctInterleavedMemSize == (uint64_t)(NBPtr->DCTPtr->Timings.DctMemSize) << 6) {
     // The whole memory range is interleaved for the DCTs with the minimum memory size
     for (i = 0; i < NBPtr->DctCount; i++) {
       DctMemLimit += DctInterleavedMemSize;