[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Nico Huber has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email )

Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
......................................................................

Patch Set 3: Code-Review+1

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/83136/comment/8ac6c028_1a781f44?usp... :
PS3, Line 10: not for PCIe device usage.
Not for DRAM either. It's simply unusable to us, right? I would
write something like "is reserved for unknown devices" (or list
the devices).

File src/soc/intel/xeon_sp/chip_gen1.c:

https://review.coreboot.org/c/coreboot/+/83136/comment/727e7cc5_0531fc80?usp... :
PS3, Line 62: 		(reserved_mmio <= sr->PciResourceMem32Limit))
Shouldn't align with the if body. i.e. either do
```
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
                (reserved_mmio <= sr->PciResourceMem32Limit))
        mmio_range(...
```
or
```
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
    (reserved_mmio <= sr->PciResourceMem32Limit))
         mmio_range(...
```

File src/soc/intel/xeon_sp/spr/ioat.c:

https://review.coreboot.org/c/coreboot/+/83136/comment/9d8f7e70_ea69c2af?usp... :
PS3, Line 143: 		(reserved_mmio <= sr->PciResourceMem32Limit)) {
Same alignment issue.

https://review.coreboot.org/c/coreboot/+/83136/comment/81361cfb_b27b222c?usp... :
PS3, Line 146: 			index++;
This could be handled with an optional pointer argument to create_ioat_domain(),
to return the current index. Not sure if that would look better, though, so leaving
resolved.