Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43846 )
Change subject: soc/skylake: Enable DCI depending on devicetree configuration
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Patch Set 2: Code-Review-1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43846/2/src/soc/intel/skylake/romst...
File src/soc/intel/skylake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/43846/2/src/soc/intel/skylake/romst...
PS2, Line 295: dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
: m_t_cfg->PchDciEn = dev ? dev->enabled : 0;
:
nope, DCI does not depend on xDCI/USBOTG being enabled AFAICT. In fsp, PchDciEn controls the register ECTRL, which enables/disables the dci feature
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