Attention is currently required from: Felix Singer, Wonkyu Kim, Michał Żygowski, Benjamin Doron, Ravishankar Sarawadi, Stefan Reinauer, Angel Pons.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56171 )
Change subject: util/inteltool: Add support for Tiger Lake chips detection and GPIOs
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Patch Set 4:
(1 comment)
File util/inteltool/gpio_names/tigerlake.h:
https://review.coreboot.org/c/coreboot/+/56171/comment/c6b94638_5eef3f3a
PS4, Line 336: "Reserved",
Then, maybe these are GPP_U0, GPP_U1, GPP_U2 and GPP_U3? Possibly undocumented.
Yes, they are. Usually there's a bunch of pins marked RSVD in the PCH DS (until Cometlake, EDS after). Some of them might be connected to some of the reserved pads, or maybe the reserved pads are really NC internally. Only Intel knows... :/
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