[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/phoenix: Update XHCI events

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74280 )

(

13 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/phoenix: Update XHCI events
......................................................................

soc/amd/phoenix: Update XHCI events

Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI
to allow for XHCI events to be logged.

BUG=b:277273428
TEST=builds

Change-Id: I3ca4f84fb0f1fef8441ab6ef7b6f6348c52b2922
Signed-off-by: Jon Murphy 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74280
Reviewed-by: Eric Lai 
Reviewed-by: Karthik Ramasubramanian 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/phoenix/Kconfig
A src/soc/amd/phoenix/include/soc/xhci.h
M src/soc/amd/phoenix/xhci.c
3 files changed, 41 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Eric Lai: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig
index 5d3adec..64617f9 100644
--- a/src/soc/amd/phoenix/Kconfig
+++ b/src/soc/amd/phoenix/Kconfig
@@ -74,6 +74,7 @@
    select SOC_AMD_COMMON_BLOCK_TSC
    select SOC_AMD_COMMON_BLOCK_UART
    select SOC_AMD_COMMON_BLOCK_UCODE
+	select SOC_AMD_COMMON_BLOCK_XHCI
    select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB		# TODO: Check if this is still correct
    select SOC_AMD_COMMON_FSP_DMI_TABLES		# TODO: Check if this is still correct
    select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
diff --git a/src/soc/amd/phoenix/include/soc/xhci.h b/src/soc/amd/phoenix/include/soc/xhci.h
new file mode 100644
index 0000000..ec71ece
--- /dev/null
+++ b/src/soc/amd/phoenix/include/soc/xhci.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PHOENIX_XHCI_H
+#define AMD_PHOENIX_XHCI_H
+
+#include <device/device.h>
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 NULL
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_PHOENIX_XHCI_H */
diff --git a/src/soc/amd/phoenix/xhci.c b/src/soc/amd/phoenix/xhci.c
index 06481ed..8bb446f 100644
--- a/src/soc/amd/phoenix/xhci.c
+++ b/src/soc/amd/phoenix/xhci.c
@@ -4,6 +4,7 @@

#include <amdblocks/gpio.h>
 #include <amdblocks/smi.h>
+#include <amdblocks/xhci.h>
 #include <bootstate.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
@@ -14,13 +15,13 @@
 static const struct sci_source xhci_sci_sources[] = {
    {
    	.scimap = SMITYPE_XHC0_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
    	.direction = SMI_SCI_LVL_HIGH,
    	.level = SMI_SCI_EDG
    },
    {
    	.scimap = SMITYPE_XHC1_PME,
-		.gpe = GEVENT_31,
+		.gpe = XHCI_GEVENT,
    	.direction = SMI_SCI_LVL_HIGH,
    	.level = SMI_SCI_EDG
    }