[coreboot-gerrit] Change in coreboot[master]: mb/google/octopus/variants/garg: support LTE power sequence.

[Marco Chen (Code Review)]

Hello Marco Chen,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/34188

to review the following change.

Change subject: mb/google/octopus/variants/garg: support LTE power sequence.
......................................................................

mb/google/octopus/variants/garg: support LTE power sequence.

BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.

Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen 
---
M src/include/gpio.h
M src/lib/gpio.c
M src/mainboard/google/octopus/bootblock.c
M src/mainboard/google/octopus/smihandler.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/octopus/variants/garg/gpio.c
M src/soc/intel/common/block/gpio/gpio.c
9 files changed, 111 insertions(+), 17 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34188/1

diff --git a/src/include/gpio.h b/src/include/gpio.h
index 0a37ee7..a605f17 100644
--- a/src/include/gpio.h
+++ b/src/include/gpio.h
@@ -24,6 +24,7 @@

/* The following functions must be implemented by SoC/board code. */
 int gpio_get(gpio_t gpio);
+int gpio_get_output(gpio_t gpio);
 void gpio_set(gpio_t gpio, int value);
 void gpio_input_pulldown(gpio_t gpio);
 void gpio_input_pullup(gpio_t gpio);
diff --git a/src/lib/gpio.c b/src/lib/gpio.c
index 8ea3b5e..9e22b63 100644
--- a/src/lib/gpio.c
+++ b/src/lib/gpio.c
@@ -190,3 +190,9 @@
 {
    return 0;
 }
+
+/* Default handler returns 0 because type of gpio_t is unknown */
+__weak int gpio_get_output(gpio_t gpio)
+{
+	return 0;
+}
diff --git a/src/mainboard/google/octopus/bootblock.c b/src/mainboard/google/octopus/bootblock.c
index 0c239db..4da3e94 100644
--- a/src/mainboard/google/octopus/bootblock.c
+++ b/src/mainboard/google/octopus/bootblock.c
@@ -21,8 +21,8 @@

void bootblock_mainboard_init(void)
 {
-	const struct pad_config *pads;
-	size_t num;
+	const struct pad_config *pads, *override_pads;
+	size_t num, override_num;

lpc_configure_pads();

@@ -34,5 +34,7 @@
    mainboard_ec_init();

pads = variant_early_gpio_table(&num);
-	gpio_configure_pads(pads, num);
+	override_pads = variant_early_override_gpio_table(&override_num);
+	gpio_configure_pads_with_override(pads, num,
+			override_pads, override_num);
 }
diff --git a/src/mainboard/google/octopus/smihandler.c b/src/mainboard/google/octopus/smihandler.c
index 27928ee..a1686e2 100644
--- a/src/mainboard/google/octopus/smihandler.c
+++ b/src/mainboard/google/octopus/smihandler.c
@@ -16,15 +16,48 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <cpu/x86/smm.h>
+#include <delay.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/smm.h>
 #include <elog.h>
+#include <gpio.h>
 #include <intelblocks/smihandler.h>
 #include <soc/pm.h>
 #include <soc/gpio.h>
 #include <variant/ec.h>
 #include <variant/gpio.h>

+struct pad_config_with_delay {
+	const struct pad_config config;
+	unsigned int delay_msecs;
+};
+
+static void power_off_lte_module_if_exist(u8 slp_typ)
+{
+	if (slp_typ != ACPI_S5 || !gpio_get_output(GPIO_LTE_RESET))
+		return;
+
+	const struct pad_config_with_delay lte_power_off_gpios[] = {
+		{
+			PAD_CFG_GPO(GPIO_161, 0, DEEP), /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+			30,
+		},
+		{
+			PAD_CFG_GPO(GPIO_117, 0, DEEP), /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
+			100
+		},
+		{
+			PAD_CFG_GPO(GPIO_67, 0, DEEP), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
+			0
+		}
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) {
+		gpio_configure_pads(&lte_power_off_gpios[i].config, 1);
+		mdelay(lte_power_off_gpios[i].delay_msecs);
+	}
+}
+
 void mainboard_smi_gpi_handler(const struct gpi_status *sts)
 {
    if (gpi_status_get(sts, EC_SMI_GPI))
@@ -39,6 +72,8 @@
    pads = variant_sleep_gpio_table(&num, slp_typ);
    gpio_configure_pads(pads, num);

+	power_off_lte_module_if_exist(slp_typ);
+
    chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
    			MAINBOARD_EC_S5_WAKE_EVENTS);
 }
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index febf779..05b2c64 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -94,7 +94,6 @@
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
    PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
    PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
    PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
    PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */
@@ -165,7 +164,6 @@

/* PCIE_WAKE[0:3]_B */
    PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */
-	PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */
    PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */
    PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */

@@ -299,6 +297,12 @@
    return NULL;
 }

+const struct pad_config *__weak variant_early_override_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
 /* GPIOs needed prior to ramstage. */
 static const struct pad_config early_gpio_table[] = {
    PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
@@ -325,6 +329,14 @@
     */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1,
    			    ENPU), /* ESPI_IO1 */
+
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
+	PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */
+	/* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs
+	 * to override this pin to output low then high respectively in two
+	 * stages.
+	 */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */
 };

const struct pad_config *__weak
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
index b408403..04ccaa7 100644
--- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/gpio.h
@@ -33,6 +33,9 @@

#define GPIO_PCH_WP	GPIO_190

+/* LTE reset GPIO */
+#define GPIO_LTE_RESET	TGPIO_161
+
 /*  Memory SKU GPIOs. */
 #define MEM_CONFIG0	GPIO_68
 #define MEM_CONFIG1	GPIO_69
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
index 5374ace..33a8f52 100644
--- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/variants.h
@@ -26,6 +26,7 @@
 const struct pad_config *variant_base_gpio_table(size_t *num);
 const struct pad_config *variant_override_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_early_override_gpio_table(size_t *num);
 const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ);

/* Baseboard default swizzle. Can be reused if swizzle is same. */
diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c
index 90601ce..c589829 100644
--- a/src/mainboard/google/octopus/variants/garg/gpio.c
+++ b/src/mainboard/google/octopus/variants/garg/gpio.c
@@ -19,6 +19,12 @@
 #include <gpio.h>
 #include <soc/gpio.h>

+#define DEFAULT_OVERRIDE_GPIOS()	PAD_NC(GPIO_104, UP_20K), \
+	/* EN_PP3300_TOUCHSCREEN */ \
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, \
+				     DISPUPD), \
+	PAD_NC(GPIO_213, DN_20K), \
+
 enum {
    SKU_1_2A2C = 1,
    SKU_9_HDMI = 9,
@@ -26,17 +32,11 @@
 };

static const struct pad_config default_override_table[] = {
-	PAD_NC(GPIO_104, UP_20K),
-
-	/* EN_PP3300_TOUCHSCREEN */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
-				     DISPUPD),
-
-	PAD_NC(GPIO_213, DN_20K),
+	DEFAULT_OVERRIDE_GPIOS()
 };

static const struct pad_config hdmi_override_table[] = {
-	PAD_NC(GPIO_104, UP_20K),
+	DEFAULT_OVERRIDE_GPIOS()

/* HV_DDI1_DDC_SDA */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, NONE, DEEP, NF1, HIZCRx1,
@@ -44,12 +44,13 @@
    /* HV_DDI1_DDC_SCL */
    PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, NONE, DEEP, NF1, HIZCRx1,
    			    DISPUPD),
+};

-	/* EN_PP3300_TOUCHSCREEN */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0,
-				     DISPUPD),
+static const struct pad_config lte_override_table[] = {
+	DEFAULT_OVERRIDE_GPIOS()

-	PAD_NC(GPIO_213, DN_20K),
+	/* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+	PAD_CFG_GPO(GPIO_161, 1, DEEP),
 };

const struct pad_config *variant_override_gpio_table(size_t *num)
@@ -61,8 +62,29 @@
    case SKU_9_HDMI:
    	*num = ARRAY_SIZE(hdmi_override_table);
    	return hdmi_override_table;
+	case SKU_17_LTE:
+		*num = ARRAY_SIZE(lte_override_table);
+		return lte_override_table;
    default:
    	*num = ARRAY_SIZE(default_override_table);
    	return default_override_table;
    }
 }
+
+static const struct pad_config lte_early_override_table[] = {
+	/* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
+	PAD_CFG_GPO(GPIO_67, 1, PWROK),
+
+	/* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */
+	PAD_CFG_GPO(GPIO_117, 1, PWROK),
+
+	/* AVS_I2S1_MCLK -- PLT_RST_LTE_L */
+	PAD_CFG_GPO(GPIO_161, 0, DEEP),
+};
+
+const struct pad_config *variant_early_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(lte_early_override_table);
+
+	return lte_early_override_table;
+}
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 7ebf05a..a53e16a 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -402,6 +402,18 @@
    return !!(reg & PAD_CFG0_RX_STATE);
 }

+int gpio_get_output(gpio_t gpio_num)
+{
+	const struct pad_community *comm = gpio_get_community(gpio_num);
+	uint16_t config_offset;
+	uint32_t reg;
+
+	config_offset = pad_config_offset(comm, gpio_num);
+	reg = pcr_read32(comm->port, config_offset);
+
+	return !!(reg & PAD_CFG0_TX_STATE);
+}
+
 void gpio_set(gpio_t gpio_num, int value)
 {
    const struct pad_community *comm = gpio_get_community(gpio_num);