Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31270 )
Change subject: intel/spi: Switch to native PCI config accessors ......................................................................
intel/spi: Switch to native PCI config accessors
Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/31270 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Matt DeVillier matt.devillier@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/spi.c M src/soc/intel/fsp_baytrail/spi.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/spi.c 6 files changed, 22 insertions(+), 191 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Werner Zeh: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 497bfd5..f7472b9 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -21,42 +21,14 @@ #include <arch/io.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <spi_flash.h> #include <spi-generic.h>
#include <soc/lpc.h> #include <soc/pci_devs.h>
-#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0; @@ -269,7 +241,7 @@ #else struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); #endif - pci_read_config_dword(dev, SBASE, &sbase); + sbase = pci_read_config32(dev, SBASE); sbase &= ~0x1ff;
return (void *)sbase; diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 66eb53a..14d1087 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -19,6 +19,8 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> +#include <device/device.h> +#include <device/pci.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <spi_flash.h> @@ -27,36 +29,6 @@ #include <stdlib.h> #include <string.h>
-#if ENV_SMM -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* ENV_SMM */ - typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0; @@ -242,7 +214,7 @@ return NULL; }
- pci_read_config_dword(dev, SBASE, &sbase); + sbase = pci_read_config32(dev, SBASE); sbase &= ~0x1ff;
return (void *)sbase; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index de3d061..5280967 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -20,42 +20,14 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <spi_flash.h> #include <spi-generic.h> #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/spi.h>
-#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0; @@ -271,7 +243,7 @@ #endif ich9_spi_regs *ich9_spi;
- pci_read_config_dword(dev, 0xf0, &rcba); + rcba = pci_read_config32(dev, 0xf0); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); @@ -289,9 +261,9 @@ ich_set_bbar(0);
/* Disable the BIOS write protect so write commands are allowed. */ - pci_read_config_byte(dev, 0xdc, &bios_cntl); + bios_cntl = pci_read_config8(dev, 0xdc); bios_cntl &= ~(1 << 5); - pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); }
static void spi_init_cb(void *unused) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index a9c0454..275b038 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -22,42 +22,14 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <spi_flash.h> #include <spi-generic.h>
#include <soc/lpc.h> #include <soc/pci_devs.h>
-#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0; @@ -258,7 +230,7 @@ #else struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); #endif - pci_read_config_dword(dev, SBASE, &sbase); + sbase = pci_read_config32(dev, SBASE); sbase &= ~0x1ff;
return (void *)sbase; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 60c0b8d..1d871d2 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -24,6 +24,7 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> #include <device/pci.h> #include <spi_flash.h>
@@ -34,36 +35,6 @@ #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
- -#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - static int spi_is_multichip(void);
typedef struct spi_slave ich_spi_slave; @@ -308,7 +279,7 @@ struct device *dev = pcidev_on_root(31, 0); #endif
- pci_read_config_dword(dev, 0xf0, &rcba); + rcba = pci_read_config32(dev, 0xf0); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) { @@ -356,10 +327,10 @@ ich_set_bbar(0);
/* Disable the BIOS write protect so write commands are allowed. */ - pci_read_config_byte(dev, 0xdc, &bios_cntl); + bios_cntl = pci_read_config8(dev, 0xdc); /* Deassert SMM BIOS Write Protect Disable. */ bios_cntl &= ~(1 << 5); - pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); + pci_write_config8(dev, 0xdc, bios_cntl | 0x1); }
static void spi_init_cb(void *unused) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index e10072a..227422b 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -21,6 +21,8 @@ #include <delay.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h>
#include <spi_flash.h> @@ -28,36 +30,6 @@
static int ich_status_poll(u16 bitmask, int wait_til_set);
-#ifdef __SMM__ -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - typedef struct spi_slave ich_spi_slave;
static int ichspi_lock = 0; @@ -349,7 +321,7 @@ #else struct device *dev = pcidev_on_root(31, 0); #endif - pci_read_config_dword(dev, 0, &ids); + ids = pci_read_config32(dev, 0); vendor_id = ids; device_id = (ids >> 16);
@@ -370,7 +342,7 @@ { uint8_t *spibase; /* SPI Base Address */ uint32_t sbase; /* SPI Base Address Register */ - pci_read_config_dword(dev, 0x54, &sbase); + sbase = pci_read_config32(dev, 0x54); /* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */ spibase = (uint8_t *)(sbase & 0xffffff00); ich10_spi_regs *ich10_spi =