[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

[Saurabh Mishra (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
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Patch Set 75:

(1 comment)

File src/soc/intel/pantherlake/systemagent.c:

https://review.coreboot.org/c/coreboot/+/83798/comment/64cb901e_e58d3b3d?usp... :
PS71, Line 33: // PCH_PRESERVERD covers:
             : 		// TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode
             : 		// eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR
             : 		// IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0
             : 		// see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h
> Sure, i have removed the comments.

Done