[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status

[Werner Zeh (Code Review)]

Attention is currently required from: Subrata Banik.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63625 )

Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
......................................................................

Patch Set 6:

(1 comment)

File src/soc/intel/common/block/fast_spi/fast_spi.c:

https://review.coreboot.org/c/coreboot/+/63625/comment/06fa94dc_ffd44b0d 
PS6, Line 437: SPIBAR_HSFSTS_W1C_BITS
> > I must admitt that Elkhart Lake does define bit 8 as well. Sorry for overseeing it. […]

If I see it right here on EHL bit 15 is the flash lock config bit. Setting it here is not something you want, right? And there are other settings in the lower bits of MSB that are R/W which you will set with 0xffff as well.