Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58062
to look at the new patch set (#3).
Change subject: soc/intel/common/../cse: Avoid caching of CSE BAR ......................................................................
soc/intel/common/../cse: Avoid caching of CSE BAR
This patch ensures all attempts to read CSE BAR is performing PCI config space read and returning the BAR value rather than using cached value.
This refactoring is useful to read BAR of all CSE devices rather than just HECI 1 alone.
Additionally, change the return type of get_cse_bar() from `uintptr_t` to `void *` to avoid typecasting while calling read32/write32 functions.
BUG=b:200644229 TEST=Able to build and boot ADLRVP where CSE is able to perform PCI enumeration and send the EOP message at post.
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: Id4ecc9006d6323b7c9d7a6af1afa5cfe63d933e5 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/58062/3