Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16613
-gerrit
commit 70b703e873eeb1a820890661f8b18daad15cf41c Author: Aaron Durbin adurbin@chromium.org Date: Fri Sep 16 11:15:49 2016 -0500
soc/intel/apollolake: cache boot media post romstage
When the boot media is memory mapped mark it as cacheable after romstage. Otherwise the boot media is uncacheable and all loads from it take longer. Loading FSP-S alone in ramstage went down to 17.5ms from 54ms.
BUG=chrome-os-partner:56656
Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33 Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/apollolake/romstage.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index ebd6287..b9733de 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -130,6 +130,11 @@ asmlinkage void car_stage_entry(void) assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+ /* Cache the memory-mapped boot media. */ + if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) + postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + run_postcar_phase(&pcf); }