[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro, Eric Lai, Felix Held.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 )

Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
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Patch Set 4:

(1 comment)

Patchset:

PS4:
> is this problem specific to google/brya or will it happen on all boards using the same soc? if the latter is the case, this should probably be done in the corresponding soc code's smi sleep handler

@Felix, so far we have only seen this issue with ADL-P and ADL-N chrome ref designs and Intel is investigating further to root cause and may be once they provide the TA for this issue, it can re-land into the SOC code. At this moment, don't want to disturb other devices with ADL-SoC unless issue is prove there.

WDYT about this approach ?