Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63960 )
Change subject: soc/amd/common/block/psp: move mbox struct to generation-specific code ......................................................................
soc/amd/common/block/psp: move mbox struct to generation-specific code
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those definitions from the common psp_def.h to the specific psp_gen[1,2].c files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Fred Reitberger reitbergerfred@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen1.c M src/soc/amd/common/block/psp/psp_gen2.c 3 files changed, 33 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h index 11686aa..f171efe 100644 --- a/src/soc/amd/common/block/psp/psp_def.h +++ b/src/soc/amd/common/block/psp/psp_def.h @@ -29,38 +29,6 @@ #define CORE_2_PSP_MSG_38_OFFSET 0x10998 #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(12)
-/* generic PSP interface status, v1 */ -#define PSPV1_STATUS_INITIALIZED BIT(0) -#define PSPV1_STATUS_ERROR BIT(1) -#define PSPV1_STATUS_TERMINATED BIT(2) -#define PSPV1_STATUS_HALT BIT(3) -#define PSPV1_STATUS_RECOVERY BIT(4) - -/* psp_mbox consists of hardware registers beginning at PSPx000070 - * mbox_command: BIOS->PSP command, cleared by PSP when complete - * mbox_status: BIOS->PSP interface status - * cmd_response: pointer to command/response buffer - */ -struct pspv1_mbox { - u32 mbox_command; - u32 mbox_status; - u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ -} __packed; - -struct pspv2_mbox { - union { - u32 val; - struct pspv2_mbox_cmd_fields { - u16 mbox_status; - u8 mbox_command; - u32 reserved:6; - u32 recovery:1; - u32 ready:1; - } __packed fields; - }; - u64 cmd_response; -} __packed; - /* command/response format, BIOS builds this in memory * mbox_buffer_header: generic header * mbox_buffer: command-specific buffer format diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 37257ba..1227c2a 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -18,6 +18,25 @@
#define PSP_MAILBOX_OFFSET 0x70
+/* generic PSP interface status, v1 */ +#define PSPV1_STATUS_INITIALIZED BIT(0) +#define PSPV1_STATUS_ERROR BIT(1) +#define PSPV1_STATUS_TERMINATED BIT(2) +#define PSPV1_STATUS_HALT BIT(3) +#define PSPV1_STATUS_RECOVERY BIT(4) + +/* + * pspv1_mbox consists of hardware registers beginning at PSPx000070 + * mbox_command: BIOS->PSP command, cleared by PSP when complete + * mbox_status: BIOS->PSP interface status + * cmd_response: pointer to command/response buffer + */ +struct pspv1_mbox { + u32 mbox_command; + u32 mbox_status; + u64 cmd_response; /* definition conflicts w/BKDG but matches agesa */ +} __packed; + static void *soc_get_mbox_address(void) { uintptr_t psp_mmio; diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index e5f23cd..67b9391 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -12,6 +12,20 @@
#define PSP_MAILBOX_OFFSET 0x10570
+struct pspv2_mbox { + union { + u32 val; + struct pspv2_mbox_cmd_fields { + u16 mbox_status; + u8 mbox_command; + u32 reserved:6; + u32 recovery:1; + u32 ready:1; + } __packed fields; + }; + u64 cmd_response; +} __packed; + static uintptr_t soc_get_psp_base_address(void) { uintptr_t psp_mmio = rdmsr(PSP_ADDR_MSR).lo;